View CS8404A_8628745.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary product information th i s doc u m e n t con t a i n s i n f orma t i o n f o r a new prod u ct . c r ys t a l sem i cond u cto r r ese r ve s t h e r i g ht to mod i fy t h is p r oduc t w i th o ut no t i c e. jan 97 ds239pp1 1 copyright ? crystal semiconductor corporation 1997 (all rights reserved) crystal semiconductor corporation p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs8403a CS8404A 96 khz digital audio transmitter features l sam p le rat e s up to 10 8 khz l supports : aes/e b u, iec 9 5 8, s/pdif, & eiaj c p -340 professi o nal and consumer f ormats l generates crc codes a nd parity bits l on-chip r s 422 line driv e r l configura b l e b uffer memory (cs840 3 a) l transpare n t mode allo w s direct connection o f c s8404a and cs 8 414 or cs8403a an d cs8413 l pin comp a tible with cs 8 401a and cs8402a descripti o n th e cs8403a and CS8404A are d i g i ta l a ud i o t ran s m i t - t er s whi c h supp o r t 96 khz s a m p le r a t e ope r at i on . the d e vi c e s e n cod e and t ra n smi t aud i o dat a acc o rd i ng t o t h e aes / ebu, iec9 5 8, s / p d i f , & e i aj c p - 340 i n t er f ace s t and a rds . t h e cs8403 a an d c s 8 404a a c cep t aud i o a n d d i g i ta l d a ta , wh i c h i s t hen mu l t i p l exe d , e ncode d and d r i ven ont o a cab l e . t h e a u dio se r i al po r t i s d oub l e b u f f - e r ed and cap a ble o f s uppo r t i ng a wid e v a r i et y o f fo r mat s . th e cs8403a h as a con f ig u rab l e i n t e r n al buf f e r memo- r y , loa d ed v i a a pa r al l e l po r t , whi c h m a y be use d to bu ff e r c h anne l s ta t us , a u x i l i ar y d a ta , a n d/o r u se r da t a. th e cs84 0 4 a mu l t i p l exe s t he chan n el , use r , and va li di t y d a ta d i r e ct l y f rom s e r i a l i np u t p i ns w i th d edi c at e d in p ut p i ns f or th e mos t i mpo r tan t c hanne l st a tus b i t s . ordering info cs84 0 3a-cs , 0 to 70 c, 24- p in p l as t ic soic cs84 0 4a-cs , 0 to 70 c, 24- p in p l as t ic soic i
cs8403a CS8404A 2 ds239pp1 table of contents: general description ..................................................................................................... 8 line drivers ........................................................................................................................ 8 cs8403a description ........................................................................................................ 8 parallel port......................................................................................................................... 8 status and control registers ............................................................................................... 8 serial port.......................................................................................................................... 11 buffer memory.................................................................................................................. 12 buffer mode 0 ............................................................................................................. 13 buffer mode 1 ............................................................................................................. 14 buffer mode 2 ............................................................................................................. 15 buffer-read and interrupt timing .................................................................................... 15 pin descriptions ............................................................................................................. 17 power supply connections ......................................................................................... 17 audio input interface .................................................................................................. 17 parallel interface ......................................................................................................... 17 transmitter interface................................................................................................... 18 CS8404A description ...................................................................................................... 19 audio serial port............................................................................................................... 19 c, u, v serial port ............................................................................................................ 21 rst and cbl (trnpt is low)......................................................................................... 21 transparent mode ............................................................................................................. 22 professional mode............................................................................................................. 23 consumer mode ................................................................................................................ 24 consumer - cd submode ................................................................................................. 25 pin descriptions ............................................................................................................. 27 power supply connections ......................................................................................... 27 audio input interface .................................................................................................. 27 control pins................................................................................................................. 28 transmitter interface................................................................................................... 29 appendix a: rs422 driver information................................................................................. 30 appendix b: mck and fsync relationship ........................................................................ 31
cs8403a CS8404A ds239pp1 3 absolute maximum ratings (gnd = 0v, all voltages with respect to ground.) notes: 1. transient currents of up to 100 ma will not cause scr latch-up. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0v, all voltages with respect to ground) notes: 2. drivers open (unloaded). the majority of power is used in the load connected to the drivers. 3. specified to operate over 0 to 70 c but tested at 25 c only. digital characteristics (t a = 25 c; vd+ = 5v 5%) notes: 4. mck for the cs8403a must be 128, 192, 256, or 384x the input word rate based on m0 and m1 in control register 2. mck for the CS8404A must be 128x the input word rate, except in transparent mode where mck is 256x the input word rate. specifications are subject to change without notice parameters symbol min max units dc power supply vd+ - 6.0 v input current, any pin except supply note 1 i in -10ma digital input voltage v ind -0.3 vd+ v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units dc voltage vd+ 4.75 5.0 5.25 v supply current note 2 i dd -310ma ambient operating temperature note 3 t a 02570c power consumption note 2 p d -1553mw parameters symbol min typ max units high-level input voltage v ih 2.0 - (vd+) + 0.3 v low-level input voltage v il -0.3 - +0.8 v high-level output voltage i o = 200 a v oh (vd+) - 1.0 - - v low-level output voltage i o = 3.2 ma v ol --0.4v input leakage current i in -1.010a master clock frequency note 4 mck - - 27.6 mhz master clock duty cycle 40 - 60 %
cs8403a CS8404A 4 ds239pp1 digital characteristics - rs422 drivers (txp, txn pins only; vd+ = 5.0v 5%) switching charactteristics - cs8403a parallel port (t a = 25 c; vd+ = 5v, inputs: logic0 = gnd, logic1 = vd+, c l = 20 pf) parameters symbol min typ max units output high voltage i oh = -30 ma v oh (vd+) - 0.7 (vd+) - 0.4 - v output low voltage i ol = 30 ma v ol -0.40.7v parameters symbol min typ max units address valid to cs low t adcss 13.5 - - ns cs high to address invalid t csadh 0--ns rd/wr valid to cs low t rwcss 10 - - ns cs low to rd/wr invalid t csrwi 35 - - ns cs low t csl 35 - - ns data valid to cs rising rd/wr low (writing) t dcssw 32 - - ns cs high to data invalid rd/wr low (writing) t csdhw 0--ns cs falling to data valid rd/wr high (reading) t csddr --35ns cs rising to data hi-z rd/wr high (reading) t csdhr 5--ns a4 - a0 d7 - d0 rd/wr writing reading adcss t csddr t csl t dcssw t csdhw t csdhr t csadh t cs d7 - d0 rd/wr csrwi t rwcss t cs8403a parallel port timing
cs8403a CS8404A ds239pp1 5 switching characteristics - serial ports (t a = 25 c; vd+ = 5v; inputs: logic0 = gnd, logic1 = vd+; c l = 20 pf) notes: 5. the input word rate (iwr) refers to the frequency at which stereo audio input sample pairs are input to the part. (a stereo pair is two audio samples.) therefore, in master mode, there are always 32 sck periods in one audio sample. 6. master mode is defined as sck and fsync being outputs. in slave mode they are inputs. in the cs8403a, control register 3 bit 1, mstr, selects master. in the CS8404A, only format 0 is master. 7. the table above assumes data is output on the falling edge and latched on the rising edge. in both parts the edge is selectable. the table is defined for the cs8403a with control register 3 bit 0, sced, set to one, and for the CS8404A in formats 4 through 7. for the other formats, the table and figure edges must be reversed (i.e. rising to falling and vice versa). 8. the diagrams show sbc rising coincident with the first rising edge of sck after fsync transitions. this is true for all modes except fsf0 & 1 both equal 1 in the cs8403a, and format 4 in the CS8404A. in these modes sbc is delayed one full sck period. parameters symbol min typ max units input word rate note 5 iwr - - 108 khz sck frequency master mode note 6 slave mode note 6 t sckf - - iwr x 64 - 12.5 hz mhz sck pulse width low slave mode note 6 t sckl 25 - - ns sck pulse width high slave mode note 6 t sckh 25 - - ns sck rising to fsync edge delay notes 6, 7 t sfds 20 - - ns sck rising to fsync edge setup notes 6, 7 t sfs 20 - - ns sdata valid to sck rising setup note 7 t sss 20 - - ns sck rising to sdata hold time note 7 t ssh 20 - - ns c, u, v valid to sck rising setup CS8404A non-cd mode notes 7, 8 t css 0--ns sck rising to c, u, v hold time CS8404A non-cd mode notes 7, 8 t scs 50 - - ns u valid to sbc rising setup note 8 CS8404A, cd mode t uss 0--ns sbc rising to u hold time note 8 CS8404A, cd mode t suh 80 - - ns rst pulse width CS8404A 150 - - ns sckh t sfs t sfds t sss t ssh t sckl t sdata sck fsync serial input timing - slave mode
cs8403a CS8404A 6 ds239pp1 sckf t sfs t sss t sdata sck fsync ssh t css t c,u,v CS8404A suh t u sbc uss t sch t non-cd mode cd mode sfds t serial input timing - master mode & c, u, v port external clock transmitter circuit see appendix b +5v 5k w 7 6 8 15 14 16 fsync sck sdata int cs rd/wr a0-a4 d0-d7 mck 5 vd+ gnd txp txn 19 18 20 17 +5v 0.1 f cs8403a audio data processor audio data processor or microcontroller figure 1. cs8403a typical connection diagram
cs8403a CS8404A ds239pp1 7 external clock transmitter circuit see appendix b 7 6 8 15 10 11 fsync sck sdata cbl c u v rst mck 5 gnd trnpt txp txn 18 24 20 17 0.1 f CS8404A microcontroller or unused channel status bits control audio data processor 8 dedicated c.s. bits +5v vd+ 19 9 16 m2 m1 23 22 m0 21 serial port mode select figure 2. CS8404A professional & consumer modes typical connection diagram external clock transmitter circuit see appendix b 7 6 8 9 10 11 fsync sck sdata v sbf u sbc rst mck 5 gnd txp txn 19 18 20 17 0.1 f CS8404A decoder subcode port channel status bits control audio data processor 8 dedicated c.s. bits +5v vd+ 15 16 m2 m1 23 22 m0 21 serial port mode select reset control figure 3. consumer cd submode typical connection diagram
cs8403a CS8404A 8 ds239pp1 general description the cs8403a/4a are monolithic cmos circuits that encode and transmit audio and digital data ac- cording to the aes/ebu, iec958 (s/pdif), and eiaj cp-340 interface standards. both chips ac- cept audio and control data separately, multiplex and biphase-mark encode the data internally, and drive it, directly or through a transformer, to a transmission line. the cs8403a is fully software programmable through a parallel port and contains buffer memory for control data, while the CS8404A has dedicated pins for the most impor- tant control bits and a serial input port for the c, u, and v bits. familiarity with the aes/ebu and iec958 speci- fications are assumed throughout this data sheet. many terms such as channel status, user data, aux- iliary data, professional mode, etc. are not defined. the application note, overview of aes/ebu digital audio interface data structures, provides an overview of the aes/ebu and iec958 specifi- cations and is included for clarity; however, it is not meant to be a complete reference, and the complete standards should be obtained from the audio engi- neering society or ansi for the aes/ebu docu- ment, and the international electrotechnical commission for the iec document. line drivers the rs422 line drivers for both the cs8403a and CS8404A are low skew, low impedance, differen- tial outputs capable of driving 110 w transmission lines with a 4 vpp signal when configured as shown in appendix a. to prevent possible short circuits, both drivers are set to ground when no master clock (mck) is provided. they can also be disabled by resetting the device (rst = low). ap- pendix a contains more information on the line drivers. a 0.1 f capacitor, with short leads, should be placed as close as possible to the vd+ and gnd pins. cs8403a description the cs8403a accepts 16- to 24-bit audio samples through a configurable serial port, and channel sta- tus, user, and auxiliary data through an 8-bit paral- lel port. the parallel port allows access to 32 bytes of internal memory which is used to store control information and buffer channel status, user, and auxiliary data. this data is multiplexed with the au- dio data from the serial port, the parity bit is gener- ated, and the bit stream is biphase-mark encoded and driven through an rs422 line driver. a block diagram of the cs8403a is shown in figure 4. in accordance with the professional definition of channel status, the crcc code (c.s. byte 23) can be internally generated. parallel port the parallel port accesses one status register, three control registers, and 28 bytes of dual port buffer memory. the address bus and rd/wr line must be valid when cs goes low. if rd/wr is low, the val- ue on the data bus will be written into the buffer memory at the specified address. if rd/wr is high, the value in the buffer memory, at the specified ad- dress, is placed on the data bus. the detailed timing for reading and writing the cs8403a can be found in the digital switching characteristics table. the memory space is allocated as shown in figure 5. there are three defined buffer memory modes se- lectable by two bits in control register 2. status and control registers upon power up the cs8403a control registers con- tain all zeros. therefore, the part is initially in reset and is muted. one's must be written to control reg- ister 2, bits rst and mute , before the part will transmit data. the remaining registers are not ini- tialized on power-up and may contain random da- ta. the first register, shown in figure 6, is the status register in which only three bits are valid. the low- er three bits contain flags indicating the position of
cs8403a CS8404A ds239pp1 9 the transmit pointer in the buffer memory. these flags may be used to avoid contention between the transmit pointer reading the data and the user up- dating the buffer memory. besides indicating the byte location being transmitted, the flags indicate the block of memory the part is currently address- ing, thereby telling the user which block is free to be written. each flag has a corresponding mask bit (control register1) which, when set, allows a transi- tion on the flag to generate a pulse on the interrupt pin. flag 0 and flag 1 cause interrupts on both edges whereas flag 2 causes an interrupt only on the ris- ing edge. timing and further explanation of the flags can be found in the buffer memory section. the two most significant bits of control register 1, bkst and trnpt, are used for transparent mode operation of the cs8403a. transparent mode is used for those applications where it is useful to maintain frame alignment between the received and transmitted audio data signals. in transparent mode (trnpt="1") the mck, fsync, sck and sdata inputs of the cs8403a can be connected to their corresponding outputs of the cs8413. in transparent mode, fsync synchronizes the trans- mitter and the receiver. the data delay through the cs8403a is set so that three frame delays occur from the input of the cs8413 to the output of the cs8403a. in transparent mode, 32 scks are re- quired per subframe. channel status block alignment between the cs8413 and the cs8403a is accomplished by set- ting bkst high at the occurrence of the flag 2 ris- ing edge of the cs8413. if fsync is a left/right signal, bkst is sampled once per frame; if fsync is a word clock, bkst is sampled once per subframe. a low to high transition of bkst (based on two successive internal samples) resets the channel status block boundary to the beginning. control register 2, shown in figure 8, contains var- ious system level functions. the two most signifi- cant bits, m1 and m0, select the frequency at the mck pin as shown in table 1. as an example, if the audio sample frequency is 44.1 khz and m0 and m1 are both zero, mck would then be 128x the audio sample rate or 5.6448 mhz. the next bit (5) in control register 2, v, indicates the validity of the current audio sample. according to the digital audio specifications, v=0 signifies that the audio signal is suitable for conversion to analog. b1 and sdata sck fsync d[0:7] a[0:3] cs rd/wr int 8 6 7 1-4,21-24 9-13 14 16 15 serial port logic interrupt control read address generator control and flags 4 x 8 buffer memory 28 x 8 audio aux c bits crc u bits validity preamble parity mux biphase mark encoder timing imck prescaler 5 mck line driver 20 17 tx p tx n figure 4. cs8403a block diagram
cs8403a CS8404A 10 ds239pp1 b0 select one of three modes for the buffer memo- ry. the different modes are shown in figure 5 and the bit combinations in table 2. more information on the different modes can be found in the buffer memory section. bit 2, crce, is the channel sta- tus crcc enable and should only be used in pro- fessional mode. when crce is high, the channel status data cyclic redundancy check characters are a d d r e s s 0 status register 0 control register 1 control register 2 control register 3 u n d e f i n e d 1 2 3 4 user data 5 6 7 8 1st four bytes of c.s. data 1st four bytes of c.s. data 1st four bytes of left c. s. data 9 a b c last 20 bytes channel status data c. s. data left c. s. data d e f 10 auxiliary data 1st four bytes of right c. s. data 11 12 13 14 right c. s. data 15 16 17 18 19 1a 1b 1c 1d 1e 1f 0123 memory mode figure 5. cs8403a buffer memory modes flag2: high for first four bytes of channel status flag1: memory mode dependent - see figure 11 flag0: high for last two bytes of user data figure 6. status register bkst: causes realignment of data block when set to 1 trnpt: selects transparent mode appropriatley setting data delay through device mask2: interrupt mask for flag2. a 1 enables the interrupt. mask1: interrupt mask for flag1. mask0: interrupt mask for flag0. figure 7. control register 1 m1: with m0, selects mck frequency. m0: with m1, selects mck frequency. v: validity bit of current sample. b1: with b0, selects the buffer memory mode b0: with b1, selects the buffer memory mode crce: channel status crc enable. professional mode only. mute : when clear, transmitted audio data is set to zero. rst : when clear, drivers are disabled, frame counters cleared. figure 8. control register 2 table 1. mclk frequencies table 2. buffer memory modes 76543210 x:00 flag2 flag1 flag0 76543210 x:01 bkst trnpt mask2 mask1 mask0 76543210 x:02 m1 m0 v b1 b0 crce mute rst m1 m0 mclk 0 0 128x input word rate 0 1 192x input word rate 1 0 256x input word rate 1 1 384x input word rate b1 b0 mode buffer memory contents 0 0 0 channel status 011 auxiliary data 1 0 2 independent channel status 113 reserved
cs8403a CS8404A ds239pp1 11 generated independently for channels a and b and are transmitted at the end of the channel status block. when mute (bit 1) is low, the transmitted audio data is forced to zero. both rst and mute are set to zero upon power up. when rst is low, the differential line drivers are set to ground and the block counters are reset to the beginning of the first block. in order to properly synchronize the rest of the cs8403a to the audio serial port, the transmit timing counters, which in- clude the flags in the status register, are not enabled after rst is set high until eight and one half sck periods after the active edge (first edge after reset is exited) of fsync. when fsync is configured as a left/right signal (fsf1=1), the counters and flags are not enabled until the right sample is being entered (during which the previous left sample is being transmit- ted). this guarantees that channel a is left and channel b is right as per the digital audio interface specs. control register 3 contains format information for the serial audio input channel. the msb is unused and the next three bits, sdf2-sdf0, select the for- mat for the serial input data with respect to fsync. there are five valid combinations of these bits as shown in figure 10. the next two bits, fsf1 and fsf0, select the format of fsync. two of the formats delineate each channel's data and do not in- dicate the particular channel. the other two formats also indicate the specific channel. the formats are shown in figure 10. bit1, mstr, determines whether fsync and sck are inputs, mstr low, or outputs, mstr high. bit0, serial clock edge se- lect, sced, selects the edge that audio data gets latched on. when sced is low, the falling edge of sck latches data in the chip and when sced is high, the rising edge is used. sdf2: with sdf0 & sdf1, select serial data format. sdf1: with sdf0 & sdf2, select serial data format. sdf0: with sdf1 & sdf2, select serial data format. fsf1: with fsf0, select fsync format. fsf0: with fsf1, select fsync format. mstr: when set, sck and fsync are outputs. sced: when set, rising edge of sck latches data. when clear, falling edge of sck latches data. figure 9. control register 3 the multitude of combinations allow for a zero glue logic interface to almost all dsps, encoder chips, and standard serial data formats. serial port the serial port is used to enter audio data and con- sists of three pins: sck, sdata, and fsync. the serial port is double buffered with sck clocking in the data from sdata, and fsync delineating au- dio samples and may define the particular channel, left or right. control register 3, shown in figure 9, configures the serial port. all the various formats are illustrat- ed in figure 10. when fsf1 is low, fsync only delineates audio samples. when fsf1 is high, it de- lineates audio samples and specifies the channel. when fsf1 is low and the port is a master (mstr = 1), fsync is a square wave output. when fsf1 is low and the port is a slave (input), fsync can be a square wave or a pulse provided the active edge, as defined in figure 10, is properly positioned with respect to sdata. bits 4, 5, and 6, sdf0-sdf2, define the format of sdata and is also described in figure 10. the five allowable formats are msb first, msb last, 16- bit lsb last, 18-bit lsb last, and 20-bit lsb last. the msb first and msb last formats accept any word length from 16 to 24 bits. the word length is controlled by providing trailing zeros in msb first mode and leading zeros in msb last mode, or by re- stricting the number of sck periods between sam- ples to the sample word length. the 16-, 18-, and 20-bit lsb-last modes require at least 16, 18, or 20 76543210 x:03 sdf2 sdf1 sdf0 fsf1 fsf0 mstr sced
cs8403a CS8404A 12 ds239pp1 sck periods per sample respectively. as a master, 32 sck periods are output per sample. fsync must be derived from mck via a dsp us- ing the same clock or by external counters. if fsync moves (jitters) with respect to mck by more than 4 mck periods, the cs8403a may reset the channel status block and flags. appendix c contains more information on the relationship of fsync and mck. buffer memory in all buffer modes, the status register and control registers are located at addresses 0-3 respectively, and the user data is buffered in locations 4-7. the parallel port can access any location in the user data buffer at any time; however, care must be taken not to modify a location when that location is being read internally. this internal reading is done through the second port of the buffer in a cyclic manner. reset initializes the internal pointer to 04h(hex). data is read from this location and stored in an 8- bit shift register which is shifted once per audio sample. (an audio sample is defined as a single channel, not a stereo pair.) the byte is transmitted lsb first, d0 being the first bit. after transmitting 8 samples, i.e. 8 user bits, the address pointer is in- cremented and the next byte of user data is loaded into the shift register. after transmitting all four bytes, 32 audio samples, the user read pointer is re- set to 04h (hex) and the cycle repeats. flag 0 in the status register monitors the position of the internal user data read pointer. when the first byte, location 04h, is read, flag 0 is set low and when the third byte, location 06h, is read, flag 0 is set high. if mask 0 in control register1 is set, a tran- sition of flag 0 will generate a low pulse on the in- terrupt pin. the value of flag 0 indicates which two bytes the part will read next, thereby indicating which two bytes are free to be updated. flag 1 is mode dependent, changing with buffer memory configuration, and is discussed in the indi- vidual buffer mode sections. 210 (bit) 000 001 010 100 110 fsf 00 01 10 11 00 01 10 11 mstr 0 0 0 0 1 1 1 1 msb first msb last lsb last 16 lsb last 18 lsb last 20 fsync input fsync input fsync input fsync input fsync output fsync output fsync output fsync output name lsb msb lsb msb lsb lsb lsb msb lsb msb lsb lsb msb lsb msb msb lsb msb lsb msb msb lsb msb lsb msb 16 bits 18 bits 20 bits 18 bits 16 bits left sample right sample 20 bits 16 clocks 16 clocks 16 clocks 16 clocks 32 clocks 32 clocks 32 clocks 32 clocks 10 (bit) sdf 24 bits, incl. aux 24 bits, incl. aux 24 bits, incl. aux 24 bits, incl. aux figure 10. cs8403a serial port sdata and fsync timing
cs8403a CS8404A ds239pp1 13 flag 2 is set high when byte 0 of the channel status, address 08h, is read, and set low when byte 4, ad- dress 0bh, is read. therefore, flag 2 high indicates the part is reading the first four bytes of channel status and the last 20 bytes are free to update. if the interrupt mask bit for flag 2 is set, the rising edge will cause an interrupt indicating the beginning of a channel status block as shown in figure 11. al- though a falling edge on flag 0 and flag 1 may cause an interrupt, the falling edge of flag 2 will not. figure 11 illustrates the flag timing for an entire channel status block which includes 24 bytes of channel status data and 384 audio samples. (this figure assumes the channel status bit is the same for the audio pair.) the lower portion of figure 11 ex- pands the first byte of channel status showing eight pairs of data with a pair defined as a frame. this is further expanded showing the first sub-frame (a0) to contain 32 bits as per the aes/ebu specifica- tions (see appendix a). when transmitting stereo, channel a is left and channel b is right. the pream- ble at the bottom of figure 11 is expanded in figure 15 to show the exact timing between flags, the interrupt pin, and internal buffer-read timing. buffer mode 0 in buffer mode 0, in addition to the user-data buffer previously discussed, one entire block of channel status data is buffered in 24 memory locations from address 08h to 1fh. this block will be transmitted flag 0 flag 1 mode 0 flag 1 modes 1 & 2 flag 2 034 78 audio data 28 29 30 31 27 23 0 1234 5678 9 1011121314 15 16 17 18 19 20 21 22 23 0 1 channel status byte (expanded) (expanded) bit frame sub-frame block (384 audio samples) see figure 15 validity user data channel status data parity bit v uc p msb aux data lsb preamble b 0 a 0 a 1 b 1 b 2 a 2 b 7 a 7 figure 11. cs8403a status register flag timing
cs8403a CS8404A 14 ds239pp1 in both channel a and channel b, one bit per frame. like the user-data buffer, the parallel port can ac- cess any location in this buffer at any time. the transmitter section reads this buffer in a cyclic non- destructive manner and stores the byte in an 8-bit shift register that is shifted once per two transmit- ted audio samples (once per frame). flag1 in the status register can be used to monitor the channel status buffer. in mode 0, flag 1 is set low when byte 0, location 08h, is read and set high when byte 16, location 18h, is read. if mask 1 in control register 1 is set, a transition on flag 1 will generate a pulse on the interrupt pin. figure 12 il- lustrates the memory read sequence for buffer mode 0 along with the flag timing. the arrows on the flags indicate an interrupt if the appropriate mask bit is set. flag 0 can cause an interrupt on ei- ther edge, which is shown only in the expanded portion of the figure for clarity. the expanded sec- tion also shows that the user buffer is reread when location 0ah of the channel status is read. buffer mode 1 in buffer mode 1, eight bytes are allocated for chan- nel status data and 16 bytes for auxiliary data as shown in figure 5. the channel status buffer, loca- tions 08h to 0fh, is divided into two sections. the first four locations always contain the first four bytes of channel status, identical to mode 0, and are read once per channel status block. the second four locations, addresses 0ch to 0fh, provide a cyclic buffer for the last 20 bytes of channel status data. similar to mode 0, transmitted channel status data will be the same for channel a and channel b (one channel status bit per frame). flag 1 and flag 2 can be used to monitor this buffer. flag 1 is set low when byte 0 of channel status data, location 08h, is read and is toggled when every other byte is read. as shown in figure 13, flag 2 is set high when byte 0, location 08h, is read and set low when byte 4, lo- cation 0ch, is read. flag 2 determines whether the channel status pointer is reading the first four-byte section or the second four-byte section, while flag 1 indicates which two bytes of the section are free to update. the auxiliary data buffer, locations 10h to 1fh, is read in a cyclic manner similar to the data buffer; however, four auxiliary data bits are transmitted per audio sample (sub-frame). since the auxiliary buffer must be read four times as often as the user data buffer and is four times as large, flag 0 can be used to monitor both. flag 0 flag 1 flag 2 (expanded) block (384 audio samples) 08 0b 1f c.s. address 01 2 34 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1 c.s. byte flag 0 08 09 0a 0b 04 05 06 07 04 05 06 07 c.s. address user address (addresses are in hex) 0c 08 figure 12. cs8403a buffer momory read sequence - mode 0
cs8403a CS8404A ds239pp1 15 buffer mode 2 in buffer mode 2, two 8-byte buffers are available for buffering both channel a and channel b chan- nel status data independently. both buffers are identical to the channel status buffer in mode 1 ex- cept that each channel can have unique channel sta- tus data. the two buffers are read simultaneously with locations 08h to 0fh transmitted in channel a and locations 10h to 17h transmitted in channel b. figure 5 contains the buffer memory modes and figure 14 illustrates the buffer read sequence for mode 2. buffer-read and interrupt timing as mentioned previously in the buffer mode sec- tions, conflicts between externally writing to the buffer ram and the cs8403a internally reading bytes of ram for transmission may be averted by us- ing the flag levels to avoid the section currently be- ing addressed by the part. interrupts occur at flag edges indicating the exact byte that the part is cur- rently reading. utilizing int along with the flags, the byte currently being read by the part can be avoided allowing access to all other bytes instead of just a section. figure 15 illustrates the timing be- tween flags, int , and the internal reading of the buffer for transmission. the master clock imck is shown as 128x fs. other mck frequencies are ini- tially divided to obtain 128x fs, defined as imck (internal mck), which is then used for all internal timing, so the timing in figure 15 is valid for all mck frequencies. when the parity bit (p) is trans- mitted, a transition on a flag causes int to go low if the appropriate mask bit is set. concurrently, the part starts reading from the internal buffer. writing to the buffer ram location being read by the part should be avoided while the internal "ram read" signal is high. flag 0 flag 1 flag 2 (expanded) block (384 audio samples) 08 0b 0c 0f 08 c.s. address 0123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 01 c.s. byte flag 0 08 09 0a 0b 04 05 06 07 04 05 06 07 c.s. address user address (addresses are in hex) 0f 0c 0f 0c 0f 0c 0f 0c 10 13,14 17 18 1b,1c 1f 10 13,14 17 18 1b,1c 1f flag 1 aux. address figure 13. cs8403a buffer memory read sequence - mode 1
cs8403a CS8404A 16 ds239pp1 flag 0 flag 1 flag 2 block (384 audio samples) left c.s. ad. 0123 4 5678 9 10111213 14 15 16 17 18 19 20 21 22 23 0 1 c.s. byte (addresses are in hex) (expanded) flag 0 08 09 0a 0b 05 06 07 04 05 06 07 left c.s. ad. user address 08 0b 0c 0f 08 0f 0c 0f 0c 0f 0c 0f 0c 10 13 14 14 10 17 14 17 14 17 14 17 14 right c.s. ad. 04 10 11 12 13 right c.s. ad. flag 1 figure 14. cs8403a buffer memory read sequence - mode 2 imck (128fs) flags 0 & 1 flag 2 int ram read txp txn cp transmit preamble figure 15. ram/buffer-read and interrupt timing
cs8403a CS8404A ds239pp1 17 pin descriptions power supply connections vd+ - positive digital power, pin 19. positive supply for the digital section. nominally +5 volts. gnd - ground, pin 18. ground for the digital section. audio input interface sck - serial clock, pin 6. serial clock for sdata pin which can be configured (via control register 3) as an input or output, and can sample data on the rising or falling edge. as an output, sck will contain 32 clocks for every audio sample. as an input, it does not need to be continuous and can be up to 15 mhz. fsync - frame sync, pin 7. delineates the serial data and may indicate the particular channel, left or right. also, fsync may be configured as an input or output. the format is based on bits in control register 3. sdata - serial data, pin 8. audio data serial input pin. parallel interface cs - chip select, pin 14. this input is active low and allows access to the 32 bytes of internal memory. the address bus and rd/wr must be valid while cs is low. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 d4 d5 d6 d7 mck sck fsync sdata a4 a3 a2 a1 data bus bit 4 data bus bit 5 data bus bit 6 data bus bit 7 master clock serial data clock frame sync serial input data address bus bit 4 address bus bit 3 address bus bit 2 address bus bit 1 d3 d2 d1 d0 txp vd+ gnd txn rd/wr int cs a0 data bus bit 3 data bus bit 2 data bus bit 1 data bus bit 0 transmit positive power ground transmit negativ e read/write selec t interrupt chip select address bus bit 0 cs8403a
cs8403a CS8404A 18 ds239pp1 rd/wr - read/write, pin 16. if rd/wr is low when cs goes active (low), the data on the data bus is written to internal memory. if rd/wr is high when cs goes active, the data in the internal memory is placed on the data bus. a4-a0 - address bus, pins 9-13. parallel port address bus that selects the internal memory location to be read from or written to. d0-d7 - data bus, pins 21-24, 1-4. parallel port data bus used to check status, write control words, or write internal buffer memory. int - interrupt, pin 15. open drain output that can signal the state of the internal buffer memory. a 5 k w resistor to vd+ is typically used to support logic gates. all bits affecting int are maskable allowing total control over the interrupt mechanism. transmitter interface mck - master clock, pin 5. clock input which defines the transmit timing. it can be configured, via control register 2, for 128, 192, 256, or 384 times the sample rate. txp, txn - differential line drivers, pins 20, 17. rs422 compatible line drivers. drivers are pulled low when part is in reset state.
cs8403a CS8404A ds239pp1 19 CS8404A description the CS8404A accepts 16- to 24-bit audio samples through a serial port configured in one of seven for- mats, provides several pins dedicated to particular channel status bits, and allows all channel status, user, and validity bits to be serially input through port pins. this data is multiplexed, the parity bit is generated, and the bit stream is biphase-mark en- coded and driven through an rs422 line driver. the CS8404A operates as a professional or con- sumer interface transmitter selectable by pin 2, pro . as a professional interface device, the dedi- cated channel status input pins are defined accord- ing to the professional standard, and the crc code (c.s. byte 23) can be internally generated. as a consumer device, the dedicated channel status input pins are defined according to the consumer standard. a submode provided under the consumer mode is compact disk, cd, mode. when transmit- ting data from a compact disk, the cd subcode port can accept cd subcode data, extract channel status information from it, and transmit it as user data. the master clock, mck, controls timing for the en- tire chip and must be 128x fs. as an example, if stereo data is input to the CS8404A at 44.1 khz, mck input must be 128 times that or 5.6448 mhz. audio serial port the audio serial port is used to enter audio data and consist of three pins: sck, sdata, and fsync. sck clocks in sdata, which is double buffered, while fsync delineates the audio samples and may indicate the particular channel, left or right. to support many different interfaces, m2, m1, and m0 select one of seven different formats for the serial port. the coding is shown in table 3 while the for- mats are shown in figure 16. format 0 and 1 are de- signed to interface with crystal adcs. format 2 communicates with motorola and ti dsps. format 3 is reserved. format 4 is compatible with the i 2 s standard. formats 5 and 6 make the CS8404A look similar to existing 16- and 18-bit dacs, and interpolation filters. format 7 is an msb-last format and is conducive to serial arith- metic. sck and fsync are outputs in format 0 and inputs in all other formats. in format 2, the ris- ing edge of fsync delineates samples and the fall- ing edge must occur a minimum of one bit period before or after the rising edge. in all formats except 2, fsync contains left/right information requiring both edges of fsync to delineate sam- ples. formats 5 and 6 require a minimum of 16- or 18-bit audio words respectively. in all formats oth- er than 5 and 6, the CS8404A can accept any word length from 16 to 24 bits by adding leading zeros in format 7 and trailing zeros in the other formats, or by restricting the number of sck periods between active edges of fsync to the sample word length. table 3. CS8404A audio port modes fsync must be derived from mck, either through a dsp using the same clock, or using counters. if fsync moves (jitters) with respect to mck by four mck periods, the internal counters and cbl may be reset. appendix b contains more informa- tion on the relationship between fsync and mck. m2 m1 m0 format 0 0 0 0 - fsync & sck output 0 0 1 1 - left/right, 16-24 bits 0 1 0 2 - word sync, 16-24 bits 0113 - reserved 100 4 - left/right, i 2 s compatible 1 0 1 5 - lsb justified, 16 bits 1 1 0 6 - lsb justified, 18 bits 1 1 1 7 - msb last, 16-24 bits
cs8403a CS8404A 20 ds239pp1 fsync (in) sck (in) sdata (in) format 7: fsync (out) sck (out) sdata (in) msb lsb msb lsb msb left right format 0: fsync (in) sck (in) sdata (in) msb lsb msb lsb msb left right format 1: fsync (in) sck (in) sdata (in) format 5: fsync (in) sck (in) sdata (in) format 6: fsync (in) sck (in) sdata (in) msb lsb msb lsb left right format 4: fsync (in) sck (in) sdata (in) format 2: format 3: (reserved) msb msb lsb msb lsb msb right msb lsb msb lsb left right lsb 16 bits 16 bits msb lsb msb lsb left right lsb 18 bits 18 bits lsb msb lsb msb left right msb left figure 16. CS8404A audio serial port formats
cs8403a CS8404A ds239pp1 21 c, u, v serial port the serial input pins for channel status (c), user (u), and validity (v) are sampled during the first bit period after the active edge of fsync for all for- mats except format 4. format 4 is sampled during the second bit period (coincident with the msb). in figure 16, the arrows on sck indicate when the c, u, and v bits are sampled. the c, u, and v bits are transmitted with the audio sample entered before the fsync edge that sampled it. the v bit, as de- fined in the audio standards, is set to zero to indi- cate the audio data is suitable for conversion to analog. therefore, when the audio data is errorred, or the data is not audio, the v bit should be set high. the channel status serial input pin (c) is not avail- able in consumer mode when the cd subcode port is enabled (fc1 = fc0 = high). any channel status data entered through the channel status serial input (c) is logically ored with the data entered through the dedicated pins or internally generated. rst and cbl (trnpt is low) when rst goes low, the differential line drivers are set to ground and the block counters are reset to the beginning of the first block. in order to properly synchronize the CS8404A to the audio serial port, the transmit timing counters, which include cbl, are not enabled after rst goes high until eight and one half sck periods after the active edge (first edge after reset is exited) of fsync. when fsync is configured as a left/right signal (all de- fined formats except 2), the counters and cbl are not enabled until the right sample is being entered (during which the previous left sample is being transmitted). this guarantees that channel a is left and channel b is right as per the digital audio inter- face specs. as shown in figure 17, channel block start output (cbl), can assist in serially inputting the c, u and v bits as cbl goes high one bit period before the first bit of the preamble of the first sub-frame of the cuv0l cuv0r cuvil left 0 preamble z vucp0l right 0 preamble y vucp0r right 191 preamble y vucp191r sdata c,u,v fsync txp txn cuv128r left 128 preamble x vucp128l vucp127r cuv1r c bit or'ed w/ c1 pin cuv0l cuv0r preamble y right 128 left 0 left 1 right 0 right 0 right 128 left 0 left 128 c bits or'ed w/ pro pin cuv191r cuv0l cuv0r cuv1l cuv191r cuv0l trnpt high trnpt low bit 0 of c.s. block byte 16 cbl aux data 0 34 7 lsb 8 left 0 - audio data preamble z 28 29 30 31 msb 27 bit sub-frame v0 p0 c0 u0 trnpt high trnpt low c bits from cpin cuv128l figure 17. cbl and tranmitter timing
cs8403a CS8404A 22 ds239pp1 channel status block is transmitted. this sub-frame contains channel status byte 0, bit 0. cbl returns low one bit period before the start of the frame that contains bit 0 of channel status byte 16. cbl is the exact inverse of flag 1 in mode 0 on the cs8403a (see figure 11). cbl is not available when the cd subcode port is enabled. figure 17 illustrates timing for stereo data input on the audio port. notice how cbl rises while the right channel data (right 0) is input, but the previ- ous left channel data (left 0) is being transmitted as the first sub-frame of the channel status block (starting with preamble z). the c, u, and v input ports only need to be valid for a short period after fsync changes. a sub-frame includes one audio sample while a frame includes a stereo pair. a channel status (c.s.) block contains 24 bytes of channel status and 384 audio samples (or 192 ste- reo pairs, or frames, of samples). figure 17 shows the cuv ports as having left and right bits (e.g. cuv0l, cuv0r). since the c.s. block is defined as 192 bits, or one bit per frame, there are actually 2 c.s. blocks, one for channel a (left) and one for channel b (right). when inputting stereo audio data, both blocks normally contain the same information, so c0l and c0r from the input port pin are both channel status bit 0 of byte 0, which is defined as professional/consumer. these first two bits from the port, c0l and c0r, are log- ically ored with the inverse of pro , since pro is a dedicated channel status pin defined as c.s. bit 0. also, if in professional mode, c1 , c6 , c7 and c9 are dedicated c.s. pins. the inverse of c1 is logi- cally ored with channel status input port bits c1l and c1r. in similar fashion, c6 , c7 and c9 are ored with their respective input bits. also, the c bits in cuv128l and cuv128r are both channel status block bit 128, which is bit 0 of channel status byte 16. transparent mode in certain applications it is desirable to receive dig- ital audio data with the cs8414 and retransmit with the CS8404A. in this case, channel status, user and validity information must pass through unal- tered. for studio environments, aes recommends that signal timing synchronization be maintained throughout the studio. frame synchronization of digital audio signals input to and output from a piece of equipment must be within 5%. the transparent mode of the CS8404A is selected by setting trnpt (pin 24) high. in this mode, the cbl pin becomes an input, allowing direct connec- tion of the outputs of the cs8414 to the inputs of the CS8404A as shown in figure 18. the transmit- ter and receiver are synchronized by the fsync signal. cbl specifies the start of a new channel sta- tus block boundary, allowing the transmit block structure to be slaved to the block structure of the receiver. in the transparent mode, c, u, and v are now transmitted with the current audio sample as shown in figure 17 (trnpt high) and the dedicat- ed channel status pins are ignored. when in the transparent mode, the propagation delay of data through the CS8404A is set so that the total propa- gation delay from the receive inputs of the cs8414 to the transmit outputs of the CS8404A is three frames. mck cbl c u v fsync sck sdata rxp rxn cs8414 trnpt txp txn v+ data processing CS8404A figure 18. transparent mode interface
cs8403a CS8404A ds239pp1 23 when fsync is a word clock (format 2), cbl is sampled when left c, u, v are sampled. when fsync is left/right, cbl is sampled when left c, u, v are sampled. the channel status block bound- ary is reset when cbl transitions from low to high (based on two successive samples of cbl). mck for the CS8404A is normally expected to be 128 times the sample frequency, in the transparent mode mck must be 256 fs. professional mode setting pro low places the CS8404A in profes- sional mode as shown in figure 19. in professional mode, channel status bit 0 is transmitted as a one and bits 1, 2, 3, 4, 6, 7, and 9 can be controlled via dedicated pins. the pins are actually the inverse of the identified bit. for example, tying the c1 pin low places a one in channel status bit 1. as shown in the application note (an22), overview of aes/ ebu digital audio interface data structures, c1 indicates audio/non-audio; c6 and c7 determine the sample frequency; and c9 allows the encoded channel mode to be stereophonic. em1 and em0 determine emphasis and encode c2 , c3 , c4 as shown in table 4. the dedicated channel status pins are read at the appropriate time and are logi- cally ored with data input on the channel status port, c. in transparent mode, these dedicated channel status pins are ignored and channel status bits are input at the c pin. table 4. emphasis encoding em1 em0 c2 c3 c4 00111 01110 10100 11000 sdata sck fsync 8 6 7 serial port logic audio aux c bits crc u bits validity preamble parity mux biphase mark encoder timing 5 mck line driver 20 17 tx p tx n 15 cbl 16 rs t c u v 10 11 9 registers 14 em0 2 pro 3 c1 13 em1 1 c7 4 c6 12 c9 trnpt 24 m2 m1 m0 23 22 21 figure 19. CS8404A block diagram - professional mode
cs8403a CS8404A 24 ds239pp1 the channel status data cyclic redundancy check character (c.s. byte 23) is always generated inde- pendently for channels a and b and is transmitted at the end of the channel status block. data should not be input through the channel status port, c, during the crcc byte time frame, since in- puts on c are logically ored with internally gen- erated data. consumer mode setting pro high places the CS8404A in consumer mode which redefines the pins as shown in figure 20. in consumer mode, channel status bit 0 is trans- mitted as a zero and channel status bits 2, 3, 8, 9, 15, 24, and 25 are controlled via dedicated pins. the pins are actually the inverse of the bit so if pin c2 is tied high, channel status bit 2 will be trans- mitted as a zero. also, fc0 and fc1 are encoded versions of channel status bits 24 and 25, which de- fine the sample frequency. when fc0 and fc1 are both high, the part is placed in a cd submode which activates the cd subcode port. this sub- mode is described in detail in the next section. ta- ble 5 describes the encoding of c24 and c25 through the fc1 and fc0 pins. according to aes/ ebu standards, c2 is copy prohibit/permit, c3 specifies pre-emphasis, c8 and c9 define the cate- gory code, and c15 identifies the generation status of the transmitted material (i.e. first generation, second generation). table 5. sample frequency encoding fc1 fc0 c24 c25 comments 0 0 0 0 44.1 khz 0 1 0 1 48.0 khz 1 0 1 1 32.0 khz 1 1 0 0 44.1 khz, cd mode sdata sck fsync 8 6 7 serial port logic audio aux c bits u bits validity preamble parity mux biphase mark encoder timing 5 mck line driver 20 17 tx p tx n 15 cbl 16 rs t c u v 10 11 9 registers 3 fc0 2 pro 4 c2 24 fc1 13 c8 1 c3 14 c9 m2 m1 m0 23 22 21 12 c15 +5v figure 20. CS8404A block diagram - consumer mode
cs8403a CS8404A ds239pp1 25 consumer - cd submode the consumer cd submode is invoked by placing the part in consumer mode (pro = high) and set- ting both fc1 and fc0 high. this mode redefines some of the pins for a cd subcode port as shown in figure 21. the cd subcode port pins, sbf and sbc, replace the c and cbl pins respectively. the user data input, u, becomes the cd subcode input. figure 22 describes the timing for the cd subcode port. when sbf is low, sbc becomes active, clocking in the subcode bits. sbf goes high for one sck period, one half sck period after the active edge of fsync for all formats (except format 4, which will be one and a half sck periods after the active edge of fsync). sbf high for more than 16 sbc periods indicates the start of a subcode block. the first, third, and fourth q bits after the start of a subcode block become channel status bits 5, 2, and 3 respectively. channel status bits are set by the dedicated pins; the category code is forced to cd. sdata sck fsync 8 6 7 serial port logic audio aux c bits u bits validity preamble parity mux biphase mark encoder timing 5 mck line driver 20 17 tx p tx n 16 rs t registers 3 fc0 2 pro 4 c2 24 fc1 13 c8 1 c3 14 c9 m2 m1 m0 23 22 21 12 c15 +5v sbf u 10 11 subcode port v 9 sbc 15 figure 21. CS8404A block diagram - consumer mode, cd submode
cs8403a CS8404A 26 ds239pp1 sbf u sbc sbf u sbc p q data latched on rising edge (expanded) rs t uv w figure 22. cd subcode port timing
cs8403a CS8404A ds239pp1 27 pin descriptions power supply connections vd+ - positive digital power, pin 19. positive supply for the digital section. nominally +5 volts. gnd - ground, pin 18. ground for the digital section. audio input interface sck - serial clock, pin 6. serial clock for sdata pin which can be configured (via the m0, m1, and m2 pins) as an input or output, and can sample data on the rising or falling edge. as an output, sck will contain 32 clocks for every audio sample. as an input, it does not need to be continuous and can be up to 15 mhz. fsync - frame sync, pin 7. delineates the serial data and may indicate the particular channel, left or right, and may be an input or output. the format is based on m0, m1, and m2 pins. sdata - serial data, pin 8. audio data serial input pin. m0, m1, m2 - serial port mode select, pins 21, 22, 23. selects the format of fsync and the sample edge of sck with respect to sdata. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 c7/c3 pro c1/fc0 c6/c2 mck sck fsync sdata v c/sbf u c9/c15 cs bit 7 / cs bit 3 professional mode cs bit 1 / freq. ctrl. 0 cs bit 6 / cs bit 2 master clock serial data clock frame sync serial input data validity input cs serial in / sc frame clock user data input cs bit 9 / cs bit 15 trnpt/fc1 m2 m1 m0 txp vd+ gnd txn rst cbl/sbc em0/c9 em1/c8 transparent / freq. ctrl. 1 serial port mode select 2 serial port mode select 1 serial port mode select 0 transmit positive power ground transmit negative master reset cs block out / sc bit cloc k emphasis 0 / cs bit 9 emphasis 1 / cs bit 8 CS8404A
cs8403a CS8404A 28 ds239pp1 control pins rst - master reset, pin 16. when low, all internal counters are reset and the line drivers are disabled, pulling low. v - validity, pin 9. validity bit serial input port. this bit is defined according to the digital audio standards wherein v=0 signifies the audio signal is suitable for conversion to analog. v=1 signifies the audio signal is not suitable for conversion to analog, i.e. invalid. v is sampled once per subframe u - user bit, pin 11. user bit serial input port is sampled once per subframe. pro - professional/consumer select, pin 2. selects between professional mode (pro low) and consumer mode (pro high). this pin defines the functionality of the next seven pins. pro must be low for transparent mode, but will have no effect on the channel status bits. c9 /c15 - channel status bit 9 / channel status bit 15, pin 12. in professional mode, c9 is the inverse of channel status bit 9 (bit 1 of byte 1). in consumer mode, c15 is the inverse of channel status bit 15 (bit 7 of byte 1). c9 /c15 are ignored in transparent mode. em0/c9 - emphasis 0 / channel status bit 9, pin 14. in professional mode, em0 and em1 encode channel status bits 2, 3, and 4. in consumer mode, c9 is the inverse of channel status bit 9 (bit 1 or byte 1). emo/c9 are ignored in transparent mode. em1/c8 - emphasis 1 / channel status bit 8, pin 13. in professional mode, em0 and em1 encode channel status bits 2, 3, and 4. in consumer mode, c8 is the inverse of channel status bit 8 (bit 0 of byte 1). em1/c8 are ignored in transparent mode. c7 /c3 - channel status bit 7 / channel status bit 3, pin 1. in professional mode, c7 is the inverse of channel status bit 7. in consumer mode, c3 is the inverse of channel status bit 3. c7 /c3 are ignored in transparent mode. c6 /c2 - channel status bit 6 / channel status bit 2, pin 4. in professional mode, c6 is the inverse of channel status bit 6. in consumer mode, c2 is the inverse of channel status bit 2. c6 /c2 are ignored in transparent mode. c1 /fc0 - channel status bit 1 / frequency control 0, pin 3. in professional mode, c1 is the inverse of channel status bit 1. in consumer mode, fc0 and fc1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). when fc0 and fc1 are both high, cd mode is selected. c1 /fc0 are ignored in transparent mode.
cs8403a CS8404A ds239pp1 29 trnpt/fc1 - transparent mode / frequency control 1, pin 24. in professional mode, setting trnpt low selects normal operation & cbl is an output. setting trnpt high, allows the CS8404A to be connected directly to a cs8414. in transparent mode, cbl is an input & mck must be at 256 fs. in consumer mode, fc0 and fc1 are encoded versions of channel status bits 24 and 25. when fc0 and fc1 are both high, cd mode is selected. c/sbf - channel status serial input / subcode frame clock, pin 10. in professional and consumer modes this pin is the channel status serial input port. in cd mode this pin inputs the cd subcode frame clock. cbl/sbc - channel status block output / subcode bit clock, pin 15. in professional and consumer modes, the channel status block output is high for the first 16 bytes of channel status. in cd mode, this pin outputs the subcode bit clock. transmitter interface mck - master clock, pin 5. clock input at 128x fs the sample frequency which defines the transmit timing. in transparent mode, mck must be 256x fs. txp, txn - differential line drivers, pins 20, 17. rs422 compatible line drivers. drivers are pulled to low when part is in reset state.
cs8403a CS8404A 30 ds239pp1 appendix a: rs422 driver information the rs422 drivers on the cs8403a and CS8404A are designed to drive both the professional and con- sumer interfaces. the aes/ebu specification for professional/broadcast use calls for a 110 w source impedance and a balanced drive capability. since the transmitter impedance is very low, a 110 w re- sistor should be placed in series with one of the transmit pins. (a 110 w resistor in parallel with the transformer would, with the receiver impedance of 110 w , provide a 55 w load to the part which is too low.) the specifications call for a balanced output drive of 2-7 volts peak-to-peak into a 110 w load with no cable attached. using the circuit in figure a1, the output of the transformer is short-circuit protected, has the proper source impedance, and provides a 5 volt peak-to-peak signal into a 110 w load. lastly, the two output pins should be attached to an xlr connector with male pins and a female shell, and with pin 1 of the connector grounded. in the case of consumer use, the specifications call for an unbalanced drive circuit with an output im- pedance of 75 w and a output drive level of 0.5 volts peak-to-peak 20% when measured across a 75 w load using no cable. the circuit shown in figure a2 only uses the txp pin and pro- vides the proper output impedance and drive level using standard 1% resistors. the connector for con- sumer would be an rca phono socket. this circuit is also short circuit protected. the txp pin may be used to drive ttl or cmos gates as shown in figure a3. this circuit may be used for optical connectors for digital audio since they are usually ttl compatible. this circuit is also useful when driving multiple digital audio out- puts since rs422 line drivers have ttl interfaces. the transformer should be capable of operating from 1.5 to 14 mhz, which is the audio data rate of 25 khz to 108 khz after biphase-mark encoding. transformers provide isolation from ground loops, 60hz noise, and common mode noise and interfer- ence. one of the important considerations when choosing transformers is minimizing shunt capaci- tance between primary and secondary windings. the higher the shunt capacitance, the lower the iso- lation between primary and secondary, and the more coupling of high frequency energy. this en- ergy appears in the form of common mode noise on the receive side ground and has the potential to de- grade analog performance. therefore, for best per- formance, shielded transformers optimized for minimum shunt capacitance should be used. the following are a few typical transformers: pulse engineering telecom products group 7250 convoy ct. san diego, ca 92111 110 w txp txn cs8403a/4a xlr 1 figure a1. professional output circuit 374 w 90.9 w txp txn cs8403a/4a rca phono figure a2. consumer output circuit txp txn cs8403a/4a ttl or cmos gate figure a3. ttl/cmos output circuit
cs8403a CS8404A ds239pp1 31 (619) 268-2400 part number: pe65612 schott corporation 1000 parkers lane rd. wayzata, mn 55391 (612) 475-1173 fax (612) 475-1786 part number: 67125450 - compatible with pulse 67128990 - lower cost 67129000 - surface mount 67129600 - single shield scientific conversions inc. 42 truman drive novato, ca. 94947 (415) 892-2323 part number: sc916-01 - single shield sc916-02 - surface mount appendix b: mck and fsync relationship fsync should be derived either directly or indi- rectly from mck. the indirect case could be a dsp, providing fsync through its serial port, us- ing the same master oscillator that generates mck. in either case, fsync's relationship to mck is fixed and does not move. since this appendix pro- vides information on what would happen if fsync did move with respect to mck, it does not apply to the majority of users. all internal timing is derived from mck. on the CS8404A, mck is always 128xfs. on the cs8403a, the external mck is programmable and is initially divided to 128xfs before being used by the part. the internal clock imck used in the fol- lowing discussion is always 128xfs regardless of the external mck pin. after rst , the cs8403a and CS8404A synchro- nize the internal timing to the audio data port, more specifically fsync, to guarantee that channel a is left channel data and channel b is right channel data as per the aes/ebu specification. if fsync moves with respect to imck, the transmitter could lose synchronization, which causes an internal re- set. figure b1 shows the structure of the serial port in- put, to the transmitter output. the audio data is se- rially shifted into r1. pld is an internal signal that parallel loads r1 into the r2 buffer, and, at the same time, the c, u, and v bits are latched. on the cs8403a, the c, u, and v bits are held in ram, whereas on the CS8404A, they are latched from ex- ternal pins. the pld signal rises on the first sck edge that can latch data. this is coincident with the latching of the msb of audio data in msb-first, left-justified modes. pld stays high for one sck period. in the CS8404A section, the arrows on sck in figure 16 indicate when pld goes high. also, sbc in the CS8404A cd submode is an external version of pld gated by the sbf input. when the part is finished transmitting the preamble of a sub-frame, the internal signal lds rises to par- allel-load r2 into r3 for transmission. after rst , the part synchronizes the audio port to imck as shown in figure b2. since pld is based on fsync and lds is based on imck, if fsync moves with respect to imck until pld and lds occur at the same time, the data would not be prop- erly loaded into r3. if lds and pld overlap, an internal reset is initiated causing the timing to re- turn to the initial state shown in figure b2.
cs8403a CS8404A 32 ds239pp1 sdata sck r1 - shift (in) register internally generated pc u v r2 - audio buffer r3 - shift (out) register CS8404A c, u, v port cs8403a internal memory i m c k 2 pld (load signal) +v d qinternal reset lds (load signal) preamble mux biphase encode driver txp txn figure b1. serial port-to-transmitter block diagram 9.5 vucp vucp 8.5 left 0 right 0 cuv0l cuv191r left 191 right 191 191l preamb. 191r preamb. sck fsync sdata CS8404A c, u, v pld imck lds txp txn cs8403a flags CS8404A cbl left 0 figure b2. serial port-to-transmitter timing (slave mode)
inches millimeters d i m m in m a x m in m a x a 0 . 093 0 . 104 2 .35 2 .65 a1 0 . 004 0 . 012 0 .10 0 .30 b 0 . 013 0 . 020 0 .33 0 .51 c 0 . 009 0 . 013 0 .23 0 .32 d 0 . 598 0 . 614 1 5.20 1 5.60 e 0 . 291 0 . 299 7 .40 7 .60 e 0 . 040 0 . 060 1 .02 1 .52 h 0 . 394 0 . 419 1 0.00 1 0.65 l 0 . 016 0 . 050 0 .40 1 .27 0 8 0 8 24l soic (300 mil body) package drawing d h e b a1 a c l s e at i ng plane 1 e

▲Up To Search▲

Price & Availability of CS8404A

	To Download CS8404A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .